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<a href=”numeric_std_unsigned_c.vhdl”>numeric_std_unsigned.vhdl</a> This package

is a “standardized” verion of “std_logic_unsigned” which appears in many vendor tools. </p> <p>

Use model:<br>
<b>use ieee.std_logic_1164.all;<br>
use ieee.numeric_std.all;<br> use ieee_proposed.numeric_std_additions.all;</b> use ieee_proposed.numeric_std_unsigned.all;</b>

</p> <p>VHDL-2008 use model:<br> <b>use ieee.numeric_std_unsigned.all;</b> </p> <p>

Dependencies: ieee.std_logic_1164, ieee.numeric_std

</p> <p> This package treats “std_logic_vector” and “std_ulogic_vector” just like the “unsigned” type in ieee.numeric_std. It has all of the funcitionality of the old “std_logic_unsigned” package with the ability to use “std_ulogic_vector”. </p> Please send feedback to <em>David W. Bishop <a href=”mailto:dbishop@vhdl.org“>dbishop@vhdl.org</a></em>. &nbsp

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